HDL Works
SPR | Title | Released | Description |
---|---|---|---|
2244 | User accepted mismatch for an FPGA pin matches to many signals | 3.1.1 | User accepted mismatch for an FPGA pin, set from the FPGA Connecton trace, with a generic name like '<RESERVED_INPUT>' and which are unconnected on the board, also matches all other pins with that name, including pins which are connected. |
2238 | No error message for missing microprocessor configuration | 3.1.1 | If a microprocessor was added to BoardTrace using a user configuration and that configuration is no longer present (project opened on other machine) no (error) message is generated. |
2236 | Incorrect sorting in the connection details | 3.1.1 | When using the OPENVPX connection mapping on a connector the sorting (both by pin number and signal name) of that connector in the Connection details is incorrect. |
2235 | ODB++ components.z file not processed | 3.1.1 | Issue a message when the ODB++ compressed file is not in the required standard Unix compress format. |
2234 | Improving handling of incorrect PCB or FPGA format | 3.1.1 | Show a red error icon when processing the PCB or FPGA file failed. |
2231 | Zuken NDF parser ignores unconnected pins | 3.1.1 | Zuken NDF parser now also adds pins that are not connected to a net and nets that are not connected to a pin. |
2213 | Missing circuit type column in HTML report | 3.1.1 | The HTML table of the connection Details doesn't show contain the circuit type (an icon) column. |
2191 | Extract voltage information from other Microsemi Libero report files. | 3.1.1 | Additional data files for voltage extraction are: <project_name>_bankrpt.rpt <project_name>_netlist_resources.rpt |
2187 | Disable beeps | 3.1.1 | User option to disable annoying beep when errors are sent to the console window |
FPGA device update | 3.1.1 | Added support for Efinix FPGAs Intel FPGA pins listed in the pinlist as "RESERVED_INPUT_WITH_WEAK_PULLUP" or "RESERVED_INPUT" are no longer marked as as being unused. |
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