Intelligent FPGA - PCB verification

The FPGA - PCB pin verification is done several steps. For generic user IO pins it is desirable that the signals on the pins have the same name in both FPGA and PCB environment. Ground pins should be connect to a ground net, while for power pins only the correct voltage is important. Unconnected or 'do not use' pins should be left unconnected on the board.

IO Checker matching rules — Matching rules

User IO verification

IO Checkers signal name matching is done in 2 steps. It starts with fuzzy matching rules for common differences between the FPGA and PCB signal names, for example bus indexes. It assumes that a signals like example_1 and example[1] or example<1> are the same.

The second step is rule based (based on regular expressions) matching. It allows the tool to validate groups of matches although individual signals can still differ. The rules can be generated automatically by the Rule Generator or manually by the user. The matching dialog allows you to directly see how many matches a rule will deliver. The automated rules approach will often match 80% to 90% of all device pins. As a last step you can set signals manually validated.

Power and Ground verification

Another mistake sometimes made is related to the power pins. The FPGA IO banks can require a different voltage than the FPGA core voltage and these banks can be programmed for different IO standards requiring a different voltage supply. IO Checker extracts the required power information from the FPGA pin file and device information and compares it with the voltage information from the PCB netlist. It recognizes most standard ways of describing a voltage value. The power verification results are shown in the Verification Window. The results are hot-linked to the corresponding pad number in the Signal View. An icon in the Signal View denotes also the power status.

Special circuits like pull-down, pull-up and decoupling circuits are can be recognized and are shown in the signal view.