The Pin view is IO Checkers most important view and shows the information extracted from the FPGA pinlist, constraint file(s) and PCB netlist. It displays up to 14 columns including pad name, bank number, the FPGA signal name, IO Type, PCB signal name and when available the constraint signal name and I/O type for each pin. In front of the PCB signal an icon is showing with recognized type of the PCB net when appropriate. It shows also voltage errors and warnings.
A severity is assigned to each line depending on the information extracted, defined rules and user interaction. Signals which have the same name in both FPGA and PCB environment are assumed correctly connected. Fuzzy matching can be used to ignore underscores and bus indicators in array names. Power pins should match by the voltage values (extracted from both pinlist and netlist). Ground pins should be connected to the ground plane.
User defined rules and user accepted mismatches can used to validate signals names which differ from FPGA to PCB, but which are correctly connected.
The view can be sorted in various ways (like by severity (errors), by pin name, by fpga signal name, by pcb signal name). Both column and rows can be hidden using filters. Each columns has its own dedicated tooltip for additional information.
The PCB netlist parsers extract the power and ground nets for the FPGA and recognizes pull-up, pull-down, decoupling, dangling and un-connected circuits. When a pull-up or decoupling circuit is recognized the connected voltage is added to the PCB signal name.
Copyright © 2004 - 2023 HDL Works