IO Checker can generate a constraint file with location and IO standard constraints. This constraint file can be used to generate the FPGA pin file. The location constraints can be generated from the PCB data and optional HDL file. When you have a PCB netlist, the signals are mapped to the PCB signal names using rules (based on regular expressions) to match the signal names between the HDL and PCB. You can also use drag & drop to create location constraints. IO standard constraints can be set by selecting the appropriate standard from a list. This list shows all standards available in the selected device.
Verification Wiring schematic symbols
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