Problems fixed in IO Checker 3.3 Revision 4
July 20, 2017


SPRTitleReleasedDescription
1577 Improved generation of HDL file from PCB data 3.3.4 Signals that are part of a vector in the netlist could still translate in single signal in the HDL.
1892 Not all IO standards are correctly set to be LVDS type 3.3.4 For a number of IO standards the IO type was not set to be LVDS type. This implies that no LVDS pair P/N check is performed for pins using this standard.
Altera 3.3.4 Added new Cyclone 10 family
Altera 3.3.4 Added MAX V family
1886 Xilinx XDC parser fails on a ';' character 3.3.3 The parser accepts comments with a '#' character. Formally there should be a command separator ';' first, but parser fails to determine the correct signal name when '; # comment' is used.
1885 CSV parser ignores comment character specified in dialog 3.3.3 The comment character cannot be set, so any comment lines will result in an error.
1884 csv2allegro interface issues incorrect messages 3.3.3 Only require the pin/pad name to be present. Don't issue a warning when enough seperators are present.
1882 To many and unclear messages in the schematic wiring interface 3.3.3 When running the schematic interface for Allegro or Altium based on the pin file and this file is incomplete 5 messages are generated for each missing pin.
Xilinx 3.3.3 First devices for the Xilinx Spartan-7 family
New devices in the Ultrascale families
1877 Drag & drop duplicates data 3.3.2 When the drag is not finished as a drop the old data is not cleared, but added to the new data.
1874 Drag & drop of PCB entry contains derived data 3.3.2 The whole PCB entry is copied to the constraint field, including voltage (from a pullup) or the signal opposite info (when present)
1873 Tooltips should not be shown for hidden pins in the device view 3.3.2 Tooltip appears while pin is not visible.
1872 Some alternate devices are incorrectly specified 3.3.2 Some device alternates for Xilinx Ultrascale devices are incorrectly specified.
Unable to start application in the background 3.3.2 The TCL interface failed to start applications in the background on Windows 7 Professional 64 bit systems
Xilinx 3.3.2 Device updates for Ultrascale families
Altera 3.3.2 Device updates for Cyclone V, Arria V, Arria 10, Stratix V families
Microsemi 3.3.2 Device updates for Igloo 2 family
1803 User PCB signal not assigned as constraint 3.3.1 Signals for which a voltage value can be determined are not used when creating VHDL or constraints.
1791 TAB characters not properly handled by Microsemi pdc reader 3.3.1 TABS are not treated as spaces.
1787 Unconnected pins not automatically matched with unconnected pcb pin 3.3.1 Unused pins in the Vivado report file are reported as "User IO' in the USE column with no signal name. In the Xilinx ISE report this used to be 'UNUSED'.
1757 Vivado Virtex pin report with SLR Regions not correctly parsed 3.3.1 Virtex devices that have multiple SLR regions have an extra column in the pin report file. This causes the IO Type and Kind data to be incorrect.
1752 Alignment and font setting for new wires can change existing (or previous added) labels 3.3.1 The global find we use will also find all other labels with the same name. These might user placed labels.
1751 Skill script fails on wires without a name 3.3.1 Allegro wiring interface did expect a wire name to be set
1735 Improve processing time of the Allegro wiring interface 3.3.1 When a project contains 100+ schematics the interface takes a long time to find the appropriate pages.
1734 Signal name ending with \G not properly processed 3.3.1 The Allegro wiring interface does not process '\' characters correctly.
1733 Signalname truncation causes duplicate signal 3.3.1 Long names like "~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP" are incorrectly trunced.
1719 Update the signal notes placed on a Allegro schematic 3.3.1 When re-running the wiring interface the notes should be removed and re-added.
1718 Use VOLTAGE property if present when extracting the netlist 3.3.1 VOLTAGE propery can be present in the Allegro BRD file and can be extracted using 'extracta'
1713 Incorrect power error on a VREF pin 3.3.1 A VREF pin which is used as regular IO pin and which has a pullup voltage on the PCB is checked as a real voltage when no FPGA pin data is present.
1695 Change default directory of Browse gadget to the current working directory 3.3.1 When no start location is set, the browse gadget uses HomeDirGet() on Windows. When using IO checker inside a framework 'PWD' is a better start location.
1649 Interface(with GUI) to adapt Allegros chip.prt files for pin swap information 3.3.1 The chip.prt file may contains PIN_GROUP for a pin. Pins that are in the same pin group may be swapped by the PCB designer.
  Altera 3.3 Updates for Arria 10 and MAX10 devices
  Xilinx 3.3 Updates for Artix-7, Kintex-7, Kintex UltraScale, Virtex-7, Virtex UltraScale and Zynq devices
  Lattice 3.3 Updates for ECP5
Home dot Company dot Products dot Sales dot Support dot HDL Corner dot Site Map
Copyright © 2004 - 2017 HDL Works