Problems fixed in EASE 8.1 Revision 8, April 8, 2015

1617 Linked libraries using relative path not resolved after relocation 8.1.8 After moving a number of projects containing linked libraries (using relative directory paths) the linked libraries will not be loaded: they still try to load the linked projects from the old location.
1625 Ease crashes when a user package contains multiple packages 8.1.8 Ease crashed when trying to determine package dependencies if a single Ease user package actually contains multiple packages that depend on each other.
1605 Project name should not be converted to lowercase 8.1.7 Project name was down cased to prevent problems in a Linux/Window environment. It is a responsibility of the designer.
1589 Missing verification message 8.1.7 No verification message if external HDL file referred by package no longer exists
1599 No slave start signal generated 8.1.7 No fsm_slave start signals are generated when a master statemachine is configured with the setting that mealy actions are being clocked and moore actions are combinatorial.
1587 Crash when creating virtual record while replacing ports on read-only entity 8.1.6 When creating a virtual record from selected ports on a read-only instance Ease will crash if you answer the question "Do you want to replace the selected ports with a new virtual port ?" with yes.
1582 Potential crash after moving objects to another library 8.1.6 After moving objects from one library to another the object identifier cache can still contain references to deleted objects. Although these references are not used from within the Ease database itself, there can be references from outside the database (e.g. user settings, top level marker). When the referred object is dereferenced this may result in a crash.
1562 Port property dialog allows type change for virtual record elements 8.1.6 When editing the properties for a port that has a virtual record type it is possible to change the type of the virtual record elements. Changes made are ignored.
  Added top_level_unit variable to Modelsim TCL script. 8.1.5 The variable denotes the toplevel unit of your project and can be used to restart the Modelsim simulator.
1559 Infinite recursion causes crash in VHDL linter 8.1.5 The VHDL lint check for tri-state assignments (Misc10) will cause a crash (infinite recursion) if a constant is referred that has an initial value containing a selected name.
1552 Generics show default values instead of actual after a component remap. 8.1.5 After a component remap the generic labels show the default value. Use 'Reconcile interface' to display the correct actual values.
1550 Corporate settings not saved correctly 8.1.5 Changes were lost the second time the settings were changed.
1548 Library import does not handle managed libraries correctly 8.1.4 When importing a library from another project that needs other libraries (that are managed), these other managed libraries are not imported correctly. The links to the VCM repository are not correct.
1547 Save As does not save managed libraries referring to a branch correctly 8.1.4 When using Save As on a project containing a managed library referring to a branch, the managed library is not saved correctly. Managed libraries referring to a tag are saved correctly.
1534 Incorrect warning about ignored default state in FSM 8.1.3 A warning is generated that the default action will be ignored when there are no actions on states. This is not correct when the FSM is fully clocked.
1533 VHDL attribute declaration for entity not imported correctly 8.1.3 When importing VHDL that contains attribute declarations at entity level they are not imported.
1532 Last modified stamp in generated HDL keeps changing 8.1.3 When generating HDL the last modified stamp keeps changing even though there are no changes made to the entity.
1529 VHDL context dependency 8.1.3 Crash during verification if context declaration contains reference to itself
1528 Connection property code uses HDL from module instead of the block diagram 8.1.3 If a Verilog Module is instantiated in a VHDL architecture the connection properties use Verilog syntax instead of VHDL.
1523 Library inconsistencies 8.1.2 After copying a library objects outside the original library may point to the copy instead of the original.
1520 Crash on incorrect code 8.1.2 VHDL Parser could crash when missing parenthesis inside procedure calls.
1510 Option to not use direct instantiations 8.1.1 It is possible to set a property on a project to use direct instantiations. This works fine in most cases, but there are some exceptions like the Xilinx Unisim library. Objects in this library cannot be instantiated using direct instantiations as there is no entity available (only a component declaration in a package).
1504 Component generics/ports color attributes are not propagated to the entity. 8.1.1 Changes of the fill/line color of component generics/ports are only performed on the component. After a reconcile interface the changes are lost.
1495 Create port with the same type on auto-add port 8.1.1 When a port is automatically created on a net connected to an component inout/buffer port the new port should get the same port mode.
1491 Also highlight port it self when doing an hierarchical highlight 8.1.1 Makes it easier to find ports which are driven by a constant value tag. They have no net connected and thus not highlighted.
1482 Rotate net label when attached to a vertical wire segment. 8.1.1 The default net label alignment should depend on the orientation of the wire segment it is attached to.
1481 Type definitions for arrays defined at architecture level not recognized by net 8.1.1 When you declare an array type at architecture level (declarations before signals), the type is not recognized as an array type by the net properties dialog, so you are not allowed to specify a range.
1480 Improve editing properties of a few entity ports 8.1.1 When a few ports are select for editing EASE still shows all ports in the entity properties port list. When +25 ports are present it is difficult to find the ones you selected.
1463 No default port data in dialog 8.1.1 When a new port is added to a component by extending an existing the wire with the wire-tool the port properties dialog is not prefilled with data.
1428 Unable to create diagram port with name of net while port is connected to the net 8.1.1 EASE will complain netname is already used.
1401 Support for VHDL-2008 context 8.1.1 Possibility to define a context and its use like a package.
1392 Allow change of multiple slices even if they have different values 8.1.1 Net connection properties: allow change of multiple slices even if they have different values
1383 Combine selected concurrent statements 8.1.1 Combine selected concurrent statements into one, while removing the others
1370 Entity a remap functionality 8.1.1 Ease way to replace one component/entity in a diagram with another will keeping the connectivity and connect-by-name tags.
1309 Copy & paste between multiple Ease instances 8.1.1 Implemented using drag & drop (not using copy & paste). It is now possible to use drag & drop of an object (entity, user package, virtual package, library) from the browser in one project and drop it on the project entry in another browser. The import will be hierarchical.
1280 Entities present in external HDL files can be modified 8.1.1 Currently entities present in external HDL files can be modified. This is strange and can lead to conflicts. If you change a port or net and propagate the changes through the hierarchy, ports on these external entities may change. However, the real definition inside the external HDL file does not change. Objects in external HDL files should be read-only be default, however it should be possible to 'unlock' them so changes can be made (e.g. to change the look and feel of the component).
612 Alignment tool 8.1.1 It would be nice if Ease has an alignment tool to align entities, states, labels into rows and columns
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