Signal View(s)

Pin signal view

The Pin signal view shows the information extracted from the FPGA pinlist, constraint file and PCB data. It shows pad name, bank number, the FPGA signal name, IO Type, PCB signal name and when available the constraint signal name and I/O type for each pin. In front of the PCB signal an icon is showing with recognized type of the PCB net when appropriate. It shows also voltage errors and warnings.

You can organize the Signal View using various sort options and filters so you can concentrate on the potential mismatches. Each columns has its own dedicated tooltip for additional information.

IO Checker Signal View
IO Checker Signal View

IO Checker PCB netlist icons The PCB netlist parsers extract the power and ground nets for the FPGA and recognize pull-up, pull-down, decoupling, dangling and un-connected circuits. When a pull-up or decoupling circuit is recognized the connected voltage is added to the PCB signal name.


The view can be sorted in various ways (like by severity (errors), by pin name, by fpga signal name, by pcb signal name). Both column and rows can be hidden using filters.

HDL View

IO Checker HDL View The HDL View is only visible when a VHDL or Verilog file has been added to the project. The view shows all toplevel ports and shows to which pad they have been assigned if this information is available. You can use this view to assign the ports to a pad in the Signal View to create or update a constraint file. You can filter already assigned ports to concentrate on the unassigned ports only.

Device View

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