FPGA Device (Alternate) View

IO Checker Device view

The device view provides a graphical representation of the FPGA package footprint. It shows the I/O banks, differential pin pairs and special pins, like power/ground and control pins. HDL signals can be assigned in the Device View to create or update a constraint file. The device view is cross linked to the signal view. The pins in the device view can be hidden depending on various criteria like unused on the PCB, power/ground, control pins, etc. The view can help you to optimize the pin assignment for critical high speed signals.

It is also useful when an alternate (migration) device is specified. In the device view it is easy to see which pins have a different functionality on both devices. The functionality of the alternate device pin is shown in the lower right corner of each pin symbol (when differing).

IO Checker Alternate Device view

The alternate device information is used when verifying a PCB netlist. Pins that are not-connected on either device should not be used on the PCB. Pins that are a ground or power pin (in one of the devices) should be connected as such. The image on the left shows an Xilinx Virtex 5 device where pin D8 (bank 124) is connected in the xc5vlx110 device but is unconnected in the xc5vlx50 device.

IO Checker Signal views Verification

Home dot Company dot Products dot Sales dot Support dot HDL Corner dot Site Map
Copyright © 2004 - 2017 HDL Works