Constraint creation and update

IO Checker HDL Signal mapping
IO Checker HDL Signal mapping

Constraint file generation

IO Checker can generate a constraint file with location and IO standard constraints. This constraint file can be used to generate the FPGA pin file. The location constraints can be generated from the PCB data and optional HDL file. When you have both the PCB netlist and HDL file, the HDL ports are mapped to the PCB signal names using rules (based on regular expressions) to match the signal names between the HDL and PCB. You can also use drag & drop to create location constraints. IO standard constraints can be set by selecting the appropriate standard from a list. This list shows all standards available in the selected device.


Fixing constraint mismatches

IO Checker can also update an existing constraint file. The original contents of your constraints file is unchanged except for the changed location or IO standard constraints. A constraint file update can be necessary to fix mismatches or when pins have been swapped. In the example on your right all new constraint assignments have a light yellow background. Using these colors it is easy to keep track of constraint changes.
IO Checker Constraint modifications
IO Checker Constraint modifications

Verification Wiring schematic symbols

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